SSDTs (Schottky barrier Source/Drain Transistors), where the highly doped source/drain of the conventional MOSFET is totally replaced with a silicide, were first reported by M. P. Lepselter and S. Sze in 1968 (see ref. 1). Recently, SSDTs have received a great deal of attention due to their excellent scaling properties and ease of fabrication and have been proposed as an alternative to traditional MOSFETs for sub-100 nm integration. See ref. 2 for example However, the drain current of a SSDT is suppressed by the Schottky barrier between source and channel, resulting in small drivability and low Ion/Ioff ratio.
The drain current increases with decreasing barrier height. The simulation results of W. Saitoh et al (ref. 3) showed that the same drivability as a conventional MOSFET can be achieved using low Schottky barriers, i.e., for the channel length Lc<30 nm devices, about 0.25 eV for P-SSDT and 0.1-0.15 eV for N-SSDT, respectively. In the literature to date, PtSi is used for P-SSDT because the electron barrier height of a PtSi/Si contact is about 0.86 eV while the corresponding hole barrier is 0.24 eV which almost meets requirements. High performance P-SSDT with PtSi has also been reported by the inventors (see ref. 4).
To date, N-SSDT has usually been based on erbium silicide because it is known that ErSi2-x has the lowest barrier height among the known silicides. This electron barrier height is about 0.28 eV (See ref. 6). However, the film morphology of ErSi2-xformed by solid-state reaction of as-deposited Er and substrate Si, is quite poor due to its island-preferred growth mode (see ref. 7), resulting in larger than theoretically expected leakage currents in the device.
The reported performance of N-SSDT is not as good as that of P-SSDT (see for example, ref. 8). Moreover, the barrier height of the ErSi2-x/Si contact is very sensitive to the residual oxygen concentration in the chamber during Er deposition and annealing. Contacts prepared in conventional vacuum displayed larger barrier heights (0.37-0.39 eV) indicating that ultra high vacuum is necessary for ErSi2-x fabrication, which makes the process inconvenient and costly.
Therefore, in order to improve the electrical performance of N-SSDT, it is very important to find a suitable way to reduce the barrier height and to improve the silicide quality for N-SSDT. In this invention, a solution to this problem is disclosed which leads to lower electron barrier height and better film morphology than that of ErSi2 formed by an otherwise same process.
Following a routine search of the patent literature, the following references of interest were found:
M. G. Jang et al, U.S. Pat. No. 6,693,294 B1, Feb. 17, 2004, “Schottky barrier tunneling transistor using thin silicon layer on insulator and method for fabrication the same”, J. P. Snyder et al, U.S. Pat. No. 6,495,882 B2, Dec. 17, 2002, “Short-channel Schottky barrier MOSFET device”, J. P. Snyder et al, U.S. Pat. No. 6,303,479 B1, Oct. 16, 2001, “Method of manufacturing a short channel FET with Schottky barrier source and drain contacts”, Omura, et al, U.S. Pat. No. 5,962,893, Oct. 5, 1999, “Schottky tunneling device”, and J. D. Welch, U.S. Pat. No. 5,663,584, Sep. 2, 1997, “Schottky barrier MOSFET systems and fabrication thereof”.